1. Field of the Invention
The present invention relates to semiconductor testing apparatus for determining whether a device under test is good or bad based on data outputted from the device under test.
2. Description of the Related Art
Pin electronics of semiconductor testing apparatus includes a comparator which captures a signal outputted from a device under test according to a strobe signal. The comparator does operation of capturing a signal synchronized with a rise (or a fall) of a strobe signal. As a time length of a signal line of each input/output pin of the device under test varies, rise timing of a strobe signal to be inputted into the comparator deviates from expected timing in an initial state. As a result, before various tests are performed on a device under test, timing calibration is performed (for example, see Japanese Patent Laid-Open No. 2-62983). With such timing calibration being performed, influence from variation in a time length of a signal line can be removed.
A semiconductor device for a high-speed serial interface that regenerates a clock signal embedded in received data and performs data receiving operation being synchronized with the regenerated clock signal has become practical recently. Such data of a clock embedded type high-speed serial interface is allowed for an uncertain width of predetermined sized timing (jitter). The conventional semiconductor testing apparatus mentioned above, however, adjusts variation in a time length of a signal line by assuming that an output timing of data is fixed, it cannot correspond to such a semiconductor device. That is to say, when output timing of data is shifted due to jitter, generating timing of a strobe signal needs to be shifted by an amount corresponding to the jitter, but conventional semiconductor testing apparatus cannot do such an adjustment.
If a clock signal can be accurately extracted from data, it is considered that generating timing of such a strobe signal can be adjusted in accord with generating timing of the clock signal. However, as variation practically occurs also in a time length of a signal line to be used for extracting a clock signal from data, a mechanism for adjusting the variation is needed. Also when a time length of the signal line exceeds a length of integer multiples of a period of a clock signal, a value corresponding to what exceeding the length will be adjusted. The adjustment value needs to be set anew for each time the frequency of the clock signal is changed. That makes the adjustment operation troublesome. Therefore, semiconductor testing apparatus that can reduce effort to adjust generating timing of a clock signal extracted from data or a time required in adjustment has been needed.